Modern computer systems often include nonvolatile semiconductor memory devices for data storage. Popular types of nonvolatile semiconductor memory devices are flash memory devices. Referring to FIG. 1, flash memory devices include an array 100 of flash memory cells 10. Each flash memory cell may be, e.g., a field effect transistor (FET). The flash memory cell 10 has a gate 11, a floating gate 21, a source 31, and a drain 41. The gate 11 operates responsive to a word line, e.g., word lines W/L0, W/L1, . . . , W/L1023. The source 31 is coupled to a sense line S/L. The drain 41 operates responsive to corresponding bit lines, e.g., bit lines B/L0, B/L1, . . . , B/L511.
The flash memory cell 10 is programmed, verified, and read by applying varying voltages to the gate 11 through a word line, e.g., W/L0, W/L1, . . . , W/L1023 and comparing the threshold voltage Vt, a drain current Id, and/or the charge stored in the floating gate 21 to a reference memory cell. Programming involves applying a program voltage to the gate 11 to program or store data into the cell array 100 by altering the charge stored in the floating gate 21 that causes a corresponding variation in a threshold voltage Vt, drain current Id, and/or charge stored. Verifying determines successful array 100 programming and typically follows programming. Reading involves reading the data from the programmed cell array 100.
Flash memory cells may store single or multiple data bits. Referring to FIG. 2A, single bit flash memory cells may have a state 1 and a state 0, indicating logic high and low, respectively. The state 1 is a bell curve defined by threshold voltages V1 and V2 where most memory cells programmed to a state 1 will exhibit threshold voltages between V1 and V2. Likewise, the state 0 is a bell curve defined by threshold voltages V3 and V4 where most memory cells programmed to a state 0 will exhibit threshold voltages between V3 and V4. The area between the states 1 and 0 is termed a separation range. A reference voltage Vref typically lies between state 1 and state 0 in the separation range. Separation ranges are theoretically unnecessary but serve to discriminate between states, e.g., states 1 and 0.
Referring to FIG. 2B, unlike single bit memory cells, multiple bit memory cells include a plurality of states, e.g., states 11, 10, 01, and 00. Flash cells that store multiple data bits are desirable because they substantially reduce bit cost. For example, memory cell density may be doubled without an attendant die increase if four data states or levels are implemented on a single cell.
The state 11 is a bell curve defined by threshold voltages V1 and V2 where most memory cells programmed to a state 11 will exhibit threshold voltages between V1 and V2. The state 10 is a bell curve defined by threshold voltages V3 and V4 where most memory cells programmed to a state 10 will exhibit threshold voltages between V3 and V4. The state 01 is a bell curve defined by threshold voltages V5 and V6 where most memory cells programmed to a state 01 will exhibit threshold voltages between V5 and V6. The state 00 is a bell curve defined by threshold voltages V7 and V8 where most memory cells programmed to a state 00 will exhibit threshold voltages between V7 and V8. Separation ranges exist between each state defining reference voltages Vref_low, Vref_medium, and Vref_high. The voltage reference Vref_low is between voltages V2 and V3 of states 11 and 10. The voltage reference Vref_medium is between voltages V4 and V5 of states 10 and 01. And the voltage reference Vref_high is between voltages V6 and V7 of states 01 and 00.
Multi bit memory cells require precise threshold voltage control. The typically higher verify voltage results in relatively narrow state distributions and broad separation ranges at the verify voltage. But when a lower read voltage is thereafter applied, the state distributions broaden and the separation ranges narrow as a result of the varying gm distributions of the storage cells. This increases the likelihood of reading errors, i.e., programming a cell, verifying that it is in the correct state, and thereafter reading it and concluding that it is in a different state.
Accordingly, a need remains for an improved multi level flash memory device and program method.